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TG68 Core In Cyclone II Questions	page 1 2 3 4 5 6 7 8 9 10

Marcel Verdaasdonk Netherlands
Posts 3991 15 May 2011 21:05	stay consequent you used a 32 bit address bus and a 16 bit data bus the 68000, 68010 and 68EC020 all have a 24 bit bus. Later versions with the exception of the 68020 used a 32 bit data bus.

Gunnar von Boehn
Germany

(Moderator)
Posts 5775
16 May 2011 07:08

Marcel Verdaasdonk wrote:

Later versions with the exception of the 68020 used a 32 bit data bus.

Marcel Verdaasdonk Netherlands
Posts 3991 16 May 2011 08:00	the 68020 is a odd duck in the 68K family if you read the data sheets there are 16 bit data bus versions and 32bit so Gunnar tread lightly on the matter before reading datasheets

Gunnar von Boehn
Germany

(Moderator)
Posts 5775
16 May 2011 09:06

Marcel Verdaasdonk wrote:

the 68020 is a odd duck in the 68K family if you read the data sheets there are 16 bit data bus versions and 32bit so Gunnar tread lightly on the matter before reading datasheets

Marcel, if you continue like this then one day we have to award you with a Bullshit award. :-D

Marcel Verdaasdonk
Netherlands

Posts 3991
16 May 2011 09:20

Gunnar von Boehn wrote:

Marcel Verdaasdonk wrote:

the 68020 is a odd duck in the 68K family if you read the data sheets there are 16 bit data bus versions and 32bit so Gunnar tread lightly on the matter before reading datasheets

Marcel, if you continue like this then one day we have to award you with a Bullshit award. :-D

Hm, Gunnar if you'll give it to me in person i will accept it.
Besides i just woke up back then and posting a RTFM would have been more appropriate since i saw my folly after your reply

68000 68010 68EC020 - 24A 16D
68020 - 32A 16D
68030 68040 68060 - 32A 32D

Happy now Gunnar?

Jakob Eriksson
Sweden

(Moderator)
Posts 1097
16 May 2011 09:59

"Data bus width is also increased to 32 bits, though if necessary the 68020 can work with 8- and 16-bit data buses." EXTERNAL LINK
Sorry. ;-)

I would also accept a bullshit award any day from Gunnar if given in person. :-)

Marcel Verdaasdonk Netherlands
Posts 3991 16 May 2011 11:30	Jacob be careful some models feature a static data bus width selection procedure.

Jakob Eriksson Sweden
(Moderator) Posts 1097 16 May 2011 12:15	Sure, no offence meant. :-)

Thierry Atheist
Canada

Posts 1830
16 May 2011 13:36

Gunnar von Boehn wrote:

Marcel Verdaasdonk wrote:

the 68020 is a odd duck in the 68K family if you read the data sheets there are 16 bit data bus versions and 32bit so Gunnar tread lightly on the matter before reading datasheets

Marcel, if you continue like this then one day we have to award you with a Bullshit award. :-D

Strange, I thought that by now I would absolutely OWN that, indisputably and no questions asked! ;-) :-DDD

He could be runner up, though. :-))))

Ajc ;)
United Kingdom

Posts 688
16 May 2011 19:48

Thierry Atheist wrote:

Strange, I thought that by now I would absolutely OWN that, indisputably and no questions asked! ;-) :-DDD

He could be runner up, though. :-))))

We'll have a ceremony, televised and all, just for you Thierry :D

Andy

Igor Majstorovic

Posts 51
01 Jul 2011 12:34

Ok i have working design now but without sdram controller. I need to connect memory cotroller to tg68 core but need help. I see that there are some work of integrating tg68 core and sdram controller to de1 and de2 boards but they use minimig as part of design. As i dont need to emulate paula, agnus and other chips my design can be simplest. Is there some examples of tg68 connected to sdram controller. Can someone point me to controller that i can use. And explane to me where to go on from now.

Ajc ;)
United Kingdom

Posts 688
04 Jul 2011 18:11

@Igor

Hi, you might have to post a bit more information.
If you have the (DDR?) SDRAM controller from the DE1 & DE2 versions of MiniMig then you've got everything you need, so I guess you're wondering what it is that you remove from the MiniMig to leave you with only the tg68 + SDRAM controller.
Is that correct?

Andy

Igor Majstorovic
Posts 51 04 Jul 2011 23:29	Yes :) You read my mind :)

Jakob Eriksson Sweden
(Moderator) Posts 1097 04 Jul 2011 23:55	This guy tried something similar: EXTERNAL LINK

Ajc ;)
United Kingdom

Posts 688
07 Jul 2011 20:23

igor majstorovic wrote:

Yes :) You read my mind :)

I'm sure that people could help you out a bit more but I don't know any VHDL/Verilog.

What have you already tried and what did you get stuck on?
For example; If I was going to try this I'd start by removing anything related to the chipset... mostly just hacking stuff out, then try to work out what formed the bridge from 68k -> OCS -> DDR.
Then I'd see what I could remove to get rid of OCS leaving just the connections from 68k->DDR, effectively trying to turn OCS into just a 68k to DDR bridge.

So what have you tried?

Igor Majstorovic

Posts 51
07 Nov 2011 22:43

Let me try my luck here again. Hardware part of the A600 fpga accelerator is done and you were able to see images on some other forums, but I have problems with soft part. Here is the question.
Ok i have modelsim testbench now, but I was thinking do I need some code to start the tg68, some assembly instructions for the processor to start fetching so that it can boot ? Because there is something wrong here in modelsim ?
here is the image link of modelsim wave posted at a1k
EXTERNAL LINK

Deep Sub Micron
Germany

(MX-Board Owner)
Posts 567
08 Nov 2011 13:37

We use a couple of test cases like the one below with our processor test bench. The test bench has a little set of IO register. Only the $00D0000C register is really used. This register can trigger a simulation break point if a none zero value is written to.


  ; Definitions                                   
  assert_zero     EQU     $00D0000C
  
  ; Vector base
          ORG     $0000
  _reset_init_stack       DC.L    $00001000
  _reset_init_pc          DC.L    $00000200 
  _access_fault           DC.L    $00000000                
  _addr_error             DC.L    $00000000
  _illegal_inst           DC.L    $00000000
  _divide_by_zero         DC.L    $00000000
  _chk_inst               DC.L    $00000000
  _trap_inst              DC.L    $00000000
  _privilge_violation     DC.L    $00000000
  _trace                  DC.L    $00000000
  _line_1010_emulator     DC.L    $00000000
  _line_1111_emulator     DC.L    $00000000
  _reserved_12            DC.L    $00000000
  _coprocessor_violation  DC.L    $00000000
  _format_error           DC.L    $00000000
  _uninitialized_interrupt DC.L   $00000000
  _reserved_16to23        DC.L    0,0,0,0,0,0,0,0
  _spurious_int           DC.L    $00000000        
  _lvevel1_int            DC.L    $00000000        
  _lvevel2_int            DC.L    $00000000        
  _lvevel3_int            DC.L    $00000000 
  _lvevel4_int            DC.L    $00000000       
  _lvevel5_int            DC.L    $00000000       
  _lvevel6_int            DC.L    $00000000       
  _lvevel7_int            DC.L    $00000000       
  _trap0d15_inst          DC.L    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
  _FP_exceptions          DC.L    0,0,0,0,0,0,0,0 
  _MMU_errors             DC.L    0,0,0
  _reserved_59to63        DC.L    0,0,0,0,0       
  _userdefined_64to255    DC.L    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
                          DC.L    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
                          DC.L    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
                          DC.L    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
  
          ORG     $0200
  START:                          ; first instruction of program
  
  ;       /* ADDQ, ADD, ADDA, ADDI  Test */
  
          moveq   #0,D0      ; Setup
          moveq   #-1,D1     ; Setup
          moveq   #-1,D2     ; Setup
          sub.l   A0,A0     ; Setup
          move.l  #$1000,A1 ; Setup
          move.l  #$0,(A1)  ; Setup
  
  ;       # Some AddQ Test
          addq.l  #1,D0   ; D0 == 00000001 ?
          addq.l  #1,D0   ; D0 == 00000002 ?
          addq.l  #8,D0   ; D0 == 0000000A ?
          
          addq.w  #1,D1   ; D1 == FFFF0000 ?
          addq.b  #1,D2   ; D2 == FFFFFF00 ?
          add.l   D0,D2  ;  D2 == FFFFFF0A ?
  
          sub.l   #$ffff0000,D1
          move.l  D1,assert_zero          ; test
          sub.l   #$ffffff0A,D2
          move.l  D2,assert_zero          ; test
   
          addq.l  #1,A0       ; A0 == 00000001 ?
          adda.l  D0,A0      ;  A0 == 0000000B ? 
          adda.l  #$1000,A0  ;  A0 == 0000100B ? 
          adda.w  #$2000,A0  ;  A0 == 0000300B ? 
  
          sub.l   #$0000300B,A0
          move.l  A0,assert_zero          ; test
  
          addq.l  #1,(A1)   ; 1000 => $00000001 ?
          addq.l  #1,(A1)   ; 1000 => $00000002 ?
          addq.l  #1,(A1)   ; 1000 => $00000003 ?
          addq.w  #4,(A1)   ; 1000 => $00040003 ?
          addq.b  #1,(A1)   ; 1000 => $01040003 ?
  
          addq.b  #4,(A1)   ; 1000 == $05040003 ?
          addq.b  #4,(A1)   ; 1000 == $09040003 ?
          addq.b  #7,2(A1)   ; 1000 == $09040703 ?
  
          move.l  #$09040703,D0
          sub.l   (a1),D0
          move.l  D0,assert_zero          ; test
  
          nop
          STOP #0
          end start

The EASy68K seems to be use full for the first steps. We have a memory in the test bench that can directly read Motorola S-Records file format as used by several other tools as well (Macroassembler AS, gnu objdump, srec_cat).

Igor Majstorovic
Posts 51 16 Dec 2011 23:26	Having problems to lock on clk from the a600 board. Can anyone help with configuration parameters. Clock from the board goes to clk buffer and then to clk multiplier and then to altera cyclone pll1 input and I just can't lock to that signal with signal tap. Do you have any suggestions.

Deep Sub Micron
Germany

(MX-Board Owner)
Posts 567
17 Dec 2011 09:24

Not sure what you mean by "to clk multiplier and then to altera cyclone pll1 input". Isn't a clock multiplier a PLL as well? So, are you chaining the PLLs?
Is the SignalTap input the PLL clock output or the PLL LOCK output? If it is the clock output then the acquisition clock input for SignalTap logic must be a different faster clock. Maybe it makes sense to not look at the clock directly but use a counter and look at the divided clock. It depends on what you like to measure.
To measure jitter you would need a very high reference clock.
If you need to measure the phase shift to a different clock I gets even more difficult.

Marcel Verdaasdonk Netherlands
Posts 3991 17 Dec 2011 21:27	Not perse Deep a multiplier can be done with a OR or a XOR but this has a effect of being slightly shifted against the reference signal which is bad. PLL isn't very hard but the trick is to stay sync with your reference signal.

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