We don't use TG68 so I can only make some general statements.

igor majstorovic wrote:

My questions are.   1. What are differences between Cyclone II and Cyclone III And Spartan III related to speed and compatibility?

I don't see a significant speed difference when switching between Cyclone II and Cyclone III. But this is something you can easily test yourself by selecting different target device and run synthesis again.
I have not done a speed compare between Altera and Xilinx.
Both Quartus and ISE should be able to use the same source. There are some exceptions like PLLs. And it would be good to have an eye on the ram block synthesis and usage.

igor majstorovic wrote:

2. I want to use this board based on EP2C5T144 Altera Cyclone II   Can i do something using this board   EXTERNAL LINK

It has no RAM on board but for your softcore you probably want some external RAM on board. This board requires a JTAG cable. Other boards have USB to JTAG converter on board. And the I/Os are not 5V. To use it as a 5V 68k replacement some additional level translators are required. If you can live with this and your design fits then it is a nice little thing.

igor majstorovic wrote:

3. Can i use some other boards based on some other FPGA.

Sure, why not.

igor majstorovic wrote:

4. Can it be done to connect SDRAM controller to TG68.

Yes, I think this can be done. But it is quite some work.

Some 3.3V devices are 5V tolerant, but your FPGA probably not.

doesn't documentation from devices you named enough?

You need to add a top level which merges the IN and OUT onto the same IOS.

ENTITY data_bus IS
PORT(
data_bus : inout STD_LOGIC_VECTOR (15 downto 0);
oe : IN STD_LOGIC;
input : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
output : OUT STD_LOGIC_VECTOR (15 DOWNTO 0));
END data_bus;

ARCHITECTURE signals OF data_bus IS
signal data_in : STD_LOGIC_VECTOR (15 downto 0);
signal data_out : STD_LOGIC_VECTOR (15 downto 0);
signal data_oe : STD_LOGIC;

BEGIN
PROCESS(oe)
BEGIN
IF oe = '1' THEN
data_bus <= data_out;
ELSE
data_bus <= "ZZZZZZZZZZZZZZZZ";
data_in <= data_bus;

END IF;
END PROCESS;
END signals;
-----------------------------

architecture signals of data_bus is
begin
  data_bus <= input when oe='1' else "ZZZZZZZZZZZZZZZZ";
  output <= data_bus;
end;

?

igor majstorovic wrote:

PROCESS(oe)   BEGIN     IF oe = '1' THEN       data_bus <= data_out;     ELSE       data_bus <= "ZZZZZZZZZZZZZZZZ";       data_in <= data_bus;     END IF;   END PROCESS;

Well the process statement has only "oe" in list of activation signals. So this might confuse the synthesis program and introduce a latch (in FPGA latches are bad and flipflops should be used). It is better to add all signals (a process reads) into activation list or use a clock by waiting on clock rising edge.

There is another pitfall you trapped into. The data_in is only assigned in the else condition which also introduces a latch.
Better always assign to output signals (or use a clock).

Since the latch is not possible in an IO-cell, the latch will be implemented using LE. But since these LE have no tristate buffer, the tristate bus will probably get replaced by a MUX structure, and that kind of fails.
I think there were many warnings in the synthesis log file.

The solution with concurrent assignments above looks a lot better.

IF data_oe = '1' THEN
...
...
...
But all i get is some errors like  Warning: Bidir "data_bus[9]" has no driver
I m going nowhere again...
Then i was trying to use TG68 generated components. In this code is missing something because i got only 16 pins. This code is not onnected to TG68. I know that i need to use something like
TG68_inst: TG68
  PORT MAP (
I m going crazy with this. More then 7 days i m working with this all day and night.
This is the code for now
-----------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY data_bus IS
PORT(
data_bus : inout STD_LOGIC_VECTOR (15 downto 0)
);
END data_bus;

ARCHITECTURE signals OF data_bus IS
COMPONENT TG68
  PORT
  (
  clk  :  IN STD_LOGIC;
  reset  :  IN STD_LOGIC;
  clkena_in  :  IN STD_LOGIC;
  data_in  :  IN STD_LOGIC_VECTOR(15 DOWNTO 0);
  IPL  :  IN STD_LOGIC_VECTOR(2 DOWNTO 0);
  dtack  :  IN STD_LOGIC;
  addr  :  OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
  data_out  :  OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
  as  :  OUT STD_LOGIC;
  uds  :  OUT STD_LOGIC;
  lds  :  OUT STD_LOGIC;
  rw  :  OUT STD_LOGIC;
  drive_data  :  OUT STD_LOGIC
  );
END COMPONENT;
signal data_in : STD_LOGIC_VECTOR (15 downto 0);
signal data_out : STD_LOGIC_VECTOR (15 downto 0);
signal data_oe : STD_LOGIC;

BEGIN
data_bus <= data_in when data_oe='1' else "ZZZZZZZZZZZZZZZZ";
  data_out <= data_bus;
END signals;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity datainout is
    port(
    clk          : in std_logic;
    reset        : in std_logic;
        clkena_in    : in std_logic:='1';
 
        IPL          : in std_logic_vector(2 downto 0):="111";
        dtack        : in std_logic;
        addr          : out std_logic_vector(31 downto 0);

        as            : buffer std_logic;
        uds          : buffer std_logic;
        lds          : buffer std_logic;
        rw            : buffer std_logic;
        drive_data    : out std_logic;
        datainout : inout std_logic_vector(15 downto 0)         
        );
end datainout;

ARCHITECTURE logic OF datainout IS

    COMPONENT TG68
    PORT (
      clk          : in std_logic;
    reset        : in std_logic;
        clkena_in    : in std_logic;
        data_in      : in std_logic_vector(15 downto 0);
        IPL          : in std_logic_vector(2 downto 0);
        dtack        : in std_logic;
        addr          : out std_logic_vector(31 downto 0);
        data_out      : out std_logic_vector(15 downto 0);
        as            : out std_logic;
        uds          : out std_logic;
        lds          : out std_logic;
        rw            : out std_logic;
        drive_data    : out std_logic
        );
    END COMPONENT;
 
signal data_in : STD_LOGIC_VECTOR (15 downto 0);
signal data_out : STD_LOGIC_VECTOR (15 downto 0);

BEGIN

data_in <= datainout;

TG68_inst: TG68
    PORT MAP (
        data_in => data_in,
    data_out => data_out,
    clk => clk,
    reset => reset,
    clkena_in => clkena_in,
    IPL => IPL,
    dtack => dtack,
    addr => addr,
    as => as,
    rw => rw,
    uds => uds,
    lds => lds,
        drive_data => drive_data   
        );
   
datainout(15 downto 8) <= data_out(15 downto 8) when as = '0' and rw = '0' and uds='0' else "ZZZZZZZZ";
datainout(7 downto 0) <= data_out(7 downto 0) when as = '0' and rw = '0' and lds='0' else "ZZZZZZZZ";
END;