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Claudio Wieland
Germany
(Natami Team)
Posts 703
24 Jan 2011 23:38


Marcel Verdaasdonk wrote:

I should have stated it was theoretical numbers. :/

Of course they are theoretical limits. But you can come close to it with an application optimized controller.

Thomas Hirsch
Germany
(MX-Board Owner)
Posts 647
24 Jan 2011 23:55


Team Chaos Leader wrote:

I thought the databus was 16 bits on LX and 32-bits on MX?

yes.

Outside 16/32 LX/MX
Inside 32/64 LX/MX

Outside means DDR, Inside means SDR.

Claudio Wieland
Germany
(Natami Team)
Posts 703
25 Jan 2011 08:42


I think the notion of "inside" and "outside" only confuses people. Just tell the number of current MT/s per pin plus the number of pins, and it is easy to do the math.
 
In the case of Natami MX, it is 32x400MT/s = peak 1.6GB/sec, right?

Gunnar von Boehn
Germany
(Moderator)
Posts 5775
25 Jan 2011 09:10


I think here are a number of confusions.

1) First of all, memory is today named with the transfer speed. This means E.g DDR200 has a transfer speed of 200. DDR400 has a speed of 400. DDR800 has a speed of 800.
Just forget about the memory clockrate or internal clockrate.
These 3 different clockrates that 1 and the same memory model has  will just confuse most people. If you want to know the transfer rate - look at the naming. The naming does name the transfer rate!

2) DDR3 has a longer burst length than DDR2 but its not faster at the same level. DDR2 has a longer burst length than DDR1 but its also not faster. The reason is that each element in the burst takes a cycle. Therefore a twice as long burst takes also twice as long.

3) This means DDR1 400 == has the same transfer rate as == DDR2 400.
Also DDR3 800 has the same transfer rate as DDR2 800.
 
4) The clockrates of the DDR generations are just higher.
With DDR1 you did not reach a 533 Level, and with DD2 you do not reach 1000 levels.

5) But with increasing the clockrate often features of the protocol were dropped. This means with DD1 you could do single memory access by stopping the burst. This means you could do "short" memory access. DDR2 does NOT support this anymore. DDR2 will always finish the burst - even if you only wanted to store a single byte.
This is a minor loss that such a big thing.

The feature loss from DDR2 to DDR3 is much bigger.
With DDR2 you can mask each byte. This means if you only want to store a single byte then you burst a line but you mask all the other bytes "away". DDR3 does not support this anymore.
This means with DDR3 to store a single byte your memory controller first needs to read the whole memory line, than internally combine (AND/OR) this with the single byte and then the memory controller is able to store the line back in memory.

What does this mean?
There are some situations where DDR3 really sucks and good DDR2 controller will be twice as fast a DDR3!
Because of I'm VERY VERY happy that we use DDR2 for the NATAMI.

What is the transfer rate of the NATAMI?
We have DDR400 x 32bit.
32bit == 4 byte.
400 x 4 == 1600 MB/sec

Now you need to mind that DDR ALWAYS is named with the maximum interface limit. DDR includes protocol and other overhead.
This means you do never the full 100% maximum of this number.

How close you come depends on your application / usage and the memory controlled.
- Is the controller optimized for long sequential access?
- Is the Controller optimized for random access?
- Is the controller optimized for a mix?
- Do you use the controller for what it was optimized or not?

Because of increased latencies with each DDR generation is more difficult to reach the theoretical maximum.
This means reaching 85% on a DDR1 was not uncommon.
This means 80% is a very good number for a DDR2 controlled.
This means you are in luck to reach 70% on a DDR3 controlled.

If you think these high marketing number of DDR3 are there to fool people, then you are could be right! ;-)

What does this mean for the NATAMI?
It means we have a theoretical bandwidth of 1600 MB/sec
But no application can reach this!
What you can get will vary on the application behavior.
To make your live simple and to be on the safe side.
If you want to code a game, then assume a bandwidth of 1000 MB/sec!



Team Chaos Leader
USA
(Moderator)
Posts 2094
25 Jan 2011 09:24


@Gunnar

Thank you for such a useful and informative message.


Louis Dias
USA

Posts 217
25 Jan 2011 14:59


Right, just like the Amiga 500 had a theoretical max of 3.57MB/s that was rarely ever reached.  But overall you can still compare one theoretical max to another and see that there is a great improvement.

Gunnar von Boehn
Germany
(Moderator)
Posts 5775
25 Jan 2011 15:05


Louis Dias wrote:

Right, just like the Amiga 500 had a theoretical max of 3.57MB/s that was rarely ever reached.  But overall you can still compare one theoretical max to another and see that there is a great improvement.

You mean 7MB?

Louis Dias
USA

Posts 217
25 Jan 2011 18:57


ah yes, 16 bits...

but isn't the theoretical max of DDR2-400 actually 3200MB/s?
EXTERNAL LINK

Marcel Verdaasdonk
Netherlands

Posts 3976
26 Jan 2011 05:21


that are PC numbers the PC has a 64 bit data bus since the Pentium4 IIRC.
 
  But i should explain it a little more clear DDR2 SDRAM DIMM's have a 64 databus.

Actuallly i just racall something about the PC which bring me back to No the P4 and this my previous statment was false.

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