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Marcel Verdaasdonk
Netherlands
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Posts 3976
01 Mar 2012 10:18
| Okay like we all know the Amiga's chipset has seen it's fair deal of bit banging. The addressing of these registers were byte wise hence the skipping of the Uneven numbered Addresses.
We all have been told the Natami has a 32bit chipset. I know of two methods one who is a clean clear break away.
Another which would less so. There are only a few who can answer that question, and i will not post any asumptions before i have heard their solution.
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Sascha B
Germany
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Posts 131
01 Mar 2012 12:27
| From my point of view the original chipset register for OCS/ECS/AGA are the same. Else no existing software (game/demo) would work on Natami.
Copper only knows of the 256 register ($000 to $1fe) in 16bit word width addressing + 16Bit value for each register.
The 32bit width is for the pointing register to make use of much more chipmem outside the 24bit addressing space (Minimig-AGA core also provide this).
Implementing of new function can be done in the reserved register or unused bits of working one.
Also a kind of bank switching to an intere new register area to make much more function possible can be done (such as C64 access "RAM under ROM").
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Marcel Verdaasdonk
Netherlands
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Posts 3976
01 Mar 2012 13:38
| lol, Sasha the copper uses the lowest bits for itself.
2.2, 2.4 and 2.8.1. of the 1985 HM, or Appendix B.
page 15, 17 and 27 of the 1989 HM, or again Appendix B.Besides not all addresses are between the $DFF000 and DFF1FE are used.
32 bits are not only handy when using pointers, also Data can be very handy in this format because if a unit has twice the ammount of data it can operate on, if implemented this means it has about twice the through put for the same cycle, compared to the narrower unit. This is not about new functions, it is about how the Team expands the chipset to 32 bit. (something a programmer would like to know)
Did they just make the Registers deeper, and if so how deep?
Did they use new register addresses?
Or did they do both?
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Sascha B
Germany
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Posts 131
01 Mar 2012 13:47
| I simply described how it works in current machines.
Also I dont't know the Natami expansion, who realy do by now?
Copper can access all chipsetregister to write new data into it, nothing else was mentioned, so why "lol"? ;)
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Jakob Eriksson
Sweden
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Posts 1097
01 Mar 2012 13:48
| The register layout and plan is not entirely finalized.
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Marcel Verdaasdonk
Netherlands
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Posts 3976
01 Mar 2012 13:54
| Sascha B wrote:
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Copper can access all chipsetregister to write new data into it, nothing else was mentioned, so why "lol"? ;)
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No it can not.
0x000 to 0x00E are not within the coppers address range even if you have the copper danger bit set.
Between 0x010 and 0x01E are only available to the copper if the danger bit is set.
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Marcel Verdaasdonk
Netherlands
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Posts 3976
01 Mar 2012 13:54
| Jakob Eriksson wrote:
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The register layout and plan is not entirely finalized.
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Ah!
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Sascha B
Germany
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Posts 131
01 Mar 2012 13:57
| Marcel Verdaasdonk wrote:
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No it can not.
0x000 to 0x00E are not within the coppers address range even if you have the copper danger bit set.
Between 0x010 and 0x01E are only available to the copper if the danger bit is set.
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Thats a limitation for the original hardware.
In FPGA ALL and even more register can be written by Copper. Same as more than 2MB of chipmem is possible.
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Marcel Verdaasdonk
Netherlands
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Posts 3976
01 Mar 2012 15:32
| err i think you have to ask yourself this do you really need access to those 8 registers? Copper writes data to a destination register. and of those 8, 2 are dummy addresses, and the rest are status registers which are read only!(even worse CLXDAT 0x00E, is read and clear!!!)
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Sascha B
Germany
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Posts 131
01 Mar 2012 17:31
| Marcel Verdaasdonk wrote:
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err i think you have to ask yourself this do you really need access to those 8 registers?
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Im more asking myself, what do you want with this discussion?
All info are rejected with no real purpose, only to keep it up...
Just WAIT until natami finally is available, then you will see whats possible.
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Marcel Verdaasdonk
Netherlands
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Posts 3976
01 Mar 2012 18:40
| Sasha My intention is to find out how the registers are made to inter-operate with the 32bit chipset. So it is clear for a programmers standpoint.
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Sascha B
Germany
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Posts 131
01 Mar 2012 19:30
| If the register and its value is not increased (what I think it is), the 32bit width could be used to fetch both, the register address and following data (each 16bit wide) in one bus cycle.
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Marcel Verdaasdonk
Netherlands
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Posts 3976
01 Mar 2012 22:25
| DDR2 databus is wider then that so that is a none issue until we try to go beyond 32a+32d bits.
Besides that Address bits are the least interesting because they usually are operated on internally and not fetched on the fly.
Making it rather moot to be able to fetch both in the same cycle.Besides that the Addresses in the Amiga's chipmem are 18 bits not 16!
Later revisions have 19bits for chipmem addresses.(2MB) Adding more registers to the copper can be problematic since by design the copper is blind for uneven register addresses.
Besides that in the original Amiga Design it has been assumed addresses address a byte which is not a limit in reality.
And which can be extended upward to a finite number as is needed.
This means the Blitter can have 32bits data register and at the same time register 0x00E can still be only 16bits!
The increase can be as needed for whichever unit, but this brings in a programming dilemma. This would reduce the required access to memory as twofold one some register access can be grouped, while others are large enough to delay access to memory. For instance the penalty of accessing say a CIA can be removed.
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Børge Nøst
Norway
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Posts 53
01 Mar 2012 23:46
| The AGA colour registers are banked IIRC?
I expect them to be flattened at a new address range, something like $DFFFxxxx.
Registers can live at two different addresses. You could have a new copperlist register that gives the copper some inherent new ability if you use it instead of the old one.Same goes for CIAs - 0.7MHz access at the old address, fullspeed at new address.
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Rune Stensland
Norway
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Posts 871
02 Mar 2012 09:04
| New registers are being mapped in the old area and new areas. some are in the $dff200++ area. This causes a problems for some games, since some bad coded games use this area for extra memory. The final hardware register layout is not finnished yet. But it will include extentions that you would expect from a AAA+ chipset (SAGA).
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Thomas Hirsch
Germany
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Posts 647
02 Mar 2012 11:16
| As soon as I encounter such a bad coded game there will be a SAGA/UCS enable bit somewhere. As for the "CIA speed penalty", it is needed at bfe.../bfd... but might be removed at another location. - If it turns out to me necessary.
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Sascha B
Germany
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Posts 131
03 Mar 2012 10:32
| "Double Dragon II" would be such one.
It uses $2xx/$4xx/$Axx(Ax) chipset register addressing. Also the game set a faulty DDFSTOP value and causes ECS/AGA bitplane distortion (same as Insanity Fight, Crack and many demo/cracktro), OCS ignores the set bit.
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