|
|---|
SID Hervé
France
| |
Posts 663
13 Aug 2012 19:19
| Hello I have read and reread this document EXTERNAL LINK but I do not understand the reason. Why the ECS registers (and not the AGA registers) have been chosen for the AAA project ? Thanks
| |
Samuel D Crow
USA
| | (Natami Team)
Posts 1295
13 Aug 2012 20:57
| My understanding is that the AAA chipset was designed before the AGA chipset was. The AAA chipset was so far behind schedule that it couldn't be made to work in time for release so Commodore scrapped the AAA chipset in favor of the AGA chipset.
| |
SID Hervé
France
| |
Posts 663
13 Aug 2012 22:07
| Thank you for your help. So it was not a matter relating to hardware performance. I found curious to choose the hardware compatibility with the ECS then remove it later. One thing still intrigues me, why not have chosen to let the OS manage the ECS as it had been planned for the AGA?
| |
Samuel D Crow
USA
| | (Natami Team)
Posts 1295
14 Aug 2012 00:02
| They DID choose to let the OS manage the chipset. It's just that the OS was so underdeveloped at the time that it couldn't perform as well as hardware banging code did.
| |
Nixus Minimax
Germany
| |
Posts 272
14 Aug 2012 10:07
| Samuel D Crow wrote:
|
They DID choose to let the OS manage the chipset. It's just that the OS was so underdeveloped at the time that it couldn't perform as well as hardware banging code did.
|
Yes, the overhead of the OS still was recognizable with the puny 7.2 MHz base processor configuration. Plus the OS was so underdeveloped that it couldn't protect itself from being disabled which is why people continued to ignore the OS when they could have and should have used it.
| |
SID Hervé
France
| |
Posts 663
14 Aug 2012 19:47
| The following digresses from the original topic. I think the idea of an overload indicator very attractive (chapter 2.3.3, last paragraph). Can it be seen as a future option for the NatAmi? Thanks
| |
Samuel D Crow
USA
| | (Natami Team)
Posts 1295
14 Aug 2012 23:16
| DDR2 memory has a lot more bandwidth than the Fast Page memory used by the AAA chips. Unfortunately, it requires the fetches to be a lot more sequential to take advantage of it. I think round-robin style DMA scheduling should not be used as a result. The DMAs should favor sequential accesses with 128-bit widths as much as possible. I've got a few ideas of how the SuperAGA chipset could be implemented but I'm not a hardware guy.
| |
Marcel Verdaasdonk
Netherlands
| |
Posts 3974
15 Aug 2012 00:06
| Samuel D Crow wrote:
|
DDR2 memory has a lot more bandwidth than the Fast Page memory used by the AAA chips. Unfortunately, it requires the fetches to be a lot more sequential to take advantage of it. I think round-robin style DMA scheduling should not be used as a result. The DMAs should favor sequential accesses with 128-bit widths as much as possible.
I've got a few ideas of how the SuperAGA chipset could be implemented but I'm not a hardware guy.
|
For best performance we should use a combination of Fetch queued DMA which only makes burst access and hidden RAS refresh on the end of a burst.
Fetch Queued means we would have a high latency on average, unless it happens to be a address directly after the current burst read/write in which case it would happen immediately after the current burst.
| |
SID Hervé
France
| |
Posts 663
15 Aug 2012 01:54
| If possible, I think some enhancements could be proposed with facilities for developers.
It is true that increased bandwidth is a plus. But I do not think that this indicator can interfere with how the DMA or the memory works.
I consider it as a safeguard. It might be useful for multitasking operation. For example, an application could dynamically adapt its needs according to its environment.
| |
Steve Thomas
United Kingdom
| |
Posts 177
26 Aug 2012 19:32
| SID Hervé wrote:
|
Hello
I have read and reread this document EXTERNAL LINK but I do not understand the reason.
Why the ECS registers (and not the AGA registers) have been chosen for the AAA project ?
Thanks
|
quote from pdf page 4
The AA registers are not supported in AAA. We believe that the 3.0 OS provides the
necessary control over AA and that no one need program “to the metal” on AA systems.
Additionally, some of the AA features were implemented in a less-than-ideal fashion, in order to
fit in the same RGA address space originally implemented in ECS. All AA-equivalent function
can be done much better by new AAA support than some kind of AA emulation.
end quote so they expected everyone to use the OS instead of accessing the AGA chips directly, so compatibility was not thought to be necessary.
| |
Marcel Verdaasdonk
Netherlands
| |
Posts 3974
26 Aug 2012 20:19
| @Steve it is also the reason the AGA registers are so badly documented.
| |
|
Do you have questions about the Natami?