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The diagram, as drawn shows it's rather different it's Gayle over PCI.

Perhaps i missunderstood the whole idea of backwards compatibility here.

As I see the drawing there are two IDE ports. Depending on configuration one can be master, the other slave. They are attached to the "PCI Gayle", a name I chose since this CPLDs functionality is quite similar to the original Galye.

Can you please suggest what I could do more precisely... It seems that since I know the concept the drawing is obvious to me - but not to people I want explain the system to.

Thomas if it only provides IDE it is missing a lot of what Gayle did.(this isn't meant negative)

Let's keep it to west side or amiga compatible IDE controller.
Unless it also supports PCMCIA cards and other goodies. ;)

Okay i'll list what should be improved if the diagram should be revised.

OPA, I can deduct something like operational amplifier out that others might not.
TX, transmit?

1. add a small list with a short explanation for yourself and other developers, what each block does this can also prevent and solve missunderstandings like this, legenda to the colour code. (IMHO, Documentation is a very important part, but please do not deviate from the project because i am a document fanatic)
2. don't leave room for asumptions, especialy when you expect that third party developers might interface to that specific part.

things you did right in the diagram.
1. you noted the number of pins for the header, specified connectors. (although, LAN does not specify the RJ45 connector, PCI 5V or 3.3V ?)
2. clear layout, this means the overal overview is great.
3. colour coded.

I cannot stress the point enough how important good documentation is.

The CPU card is a contingency as far as i can tell, or for those who absolutely require a MMU.
As soon as the team is content with the N68050 it will be placed in the main FPGA making the daughter board redundant. (and the system as a whole cheaper.)