| 8375 Features and Documentation | |
|---|
|
|---|
Marcel Verdaasdonk
Netherlands
| |
Posts 3991
19 Oct 2011 21:05
| I am looking for documentation on the CGS 8375 chip.
This is a Agnus revision.
To be specific i want to know how the address bus to Memory address bus decoding takes place.(MA9/DRA9 gives me headaches)
| |
Thomas Richter
Germany
| | (MX-Board Owner)
Posts 1425
19 Oct 2011 22:49
| Marcel Verdaasdonk wrote:
|
I am looking for documentation on the CGS 8375 chip.
This is a Agnus revision.
To be specific i want to know how the address bus to Memory address bus decoding takes place.(MA9/DRA9 gives me headaches)
|
What exactly do you need? Agnus/Alice has the internal chip bus for addressing the remaining custom chips, the memory bus for chip ram and the CPU bus. However, chip selection of the custom chip registers is not done in Agnus directly, i.e. Agnus does not know that it appears at 0xdff000. This is the job of Gary AFAIK.
| |
Marcel Verdaasdonk
Netherlands
| |
Posts 3991
20 Oct 2011 07:31
| Yes the address decoding happens in GARY which segments memory in spaces of 2MB each i am aware of this since GARY has been better defined then AGNUS in this matter. What i am looking for is Address bus to Memory address bus.
Especially the highest bit, MA9 or DRA9 depending on your document.
Is this a toggle between A19 and A20 which is rather odd since A19 is used for RAS.
Or is it purely A20 (A20 is needed for addressing odd addresses above 1MB(Intel)). So to be clear DRAM Address bus (Chip Mem).
| |
Asaf Ayoub
United Kingdom
| |
Posts 332
20 Oct 2011 14:01
| this page may help :
EXTERNAL LINK
also the ref links for schematics etc.
its 2011 and we still dont have a full documentation on hardware and software programming for Amiga. :-(.
| |
Marcel Verdaasdonk
Netherlands
| |
Posts 3991
20 Oct 2011 18:06
| sorry Asaf that source has been exhausted, I need the info so i can get a optimum design. Well let's do some trial and error and blow some 200Euro's on a prototype.
| |
Thomas Richter
Germany
| | (MX-Board Owner)
Posts 1425
20 Oct 2011 19:25
| Marcel Verdaasdonk wrote:
|
sorry Asaf that source has been exhausted, I need the info so i can get a optimum design.
|
Sorry, not for the 8375. What I have is the schematics of the A4000 with the 8374, but no functional description of the pin-out beyond what you already know. But is memory access/decoding in the A4000 not part of RAMSEY anyhow?
| |
Marcel Verdaasdonk
Netherlands
| |
Posts 3991
20 Oct 2011 20:04
| 8375 is used in the Amiga 500 and 500+
The schematics of the A2000(German version, before integration)
Has a lot of detail on the memory interaction.
However i do not know how it has been expanded upon.And that is what i like to know. Since i would like to know if applying Low CAS interleaving has effect, in comparison to the standard High CAS interleaving. I even think the DRA9 is a buffered A20 signal which would mean no matter at which point in the cycle we are it would be constant.
Anyhow it should have the effect that the latency at the end of the CAS cycle is hidden.
| |
Marcel Verdaasdonk
Netherlands
| |
Posts 3991
21 Oct 2011 11:25
| Solution found. EXTERNAL LINK
This with the U202 U203 PAL reference for the A3000 in the Dave Haynie archive grounds my conclusion that MA9/DRA9 is A20 during CAS.
This would be odd but does this mean during RAS MA9/DRA9 is A19 and thus fills in two functions limiting the number of addresses?
| |
|
Do you have questions about the Natami?