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| FC2-FC0 Function Codes In MC68000 | page 1 2
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Ganesh Bawaskar
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Posts 20
10 Mar 2011 08:12
| So it means 68k out FC2-FC0 only for stages 1, 4 and 6.
For the remaining stages it holds the ealier stage function codes (FC2-FC0) or doesnt generate any function codeAs you quoted:
"Access to PC-Relative : FC1=0/FC0=1" why? why this mode is considered as an instruction?
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Gunnar von Boehn
Germany
| | (Moderator)
Posts 5775
10 Mar 2011 08:20
| Ganesh Bawaskar wrote:
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As you quoted:
"Access to PC-Relative : FC1=0/FC0=1"
why? why this mode is considered as an instruction?
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No, its not an instruction.
The memoiry access does set the instruction-flag to 0, to flag that its a Data-access.
The PC-relative address mode, is for accessing constants which are embedded in the Code-memory segment.
Therefore the read has to go to the code space.
But I do NOT know any 68K system which really implement the 4 addresspaces. All systems that I know have one flat memory space.Does your system really need this?
What system is this that you re-implement?
Cheers
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Ganesh Bawaskar
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Posts 20
10 Mar 2011 08:33
| There is a one flat memory space in our case as well. As you quoted:
FC0 FC1 Instruction Read
Stage 1: 0 1 1 1
Stage 4: * * 0 1
Stage 6: 1 0 0 0
FC2 is set as your SupervisorBit in SR.
Please mind that Stage 4 can do two types of access!
Access to all normal EA : FC1=1/FC0=0
Access to PC-Relative : FC1=0/FC0=1 -------- I think
FC2 is used to indicate user/supervisor
FC1 is used to indicate instruction fetch
FC0 is used to indicate data fetch so with this FC2 FC1 FC0 Read write
stage 1: 0 1 0 1 0 user program
stage 4: 0 0 1 1 0 user data read
stage 6: 0 0 1 0 1 user data write but you are saying it can out FC1-FC0 as 10/01 in stage 4.
how it is possible? i mean i didnt got you Thanks
Ganesh
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Thomas Richter
Germany
| | (MX-Board Owner)
Posts 1425
10 Mar 2011 08:40
| Ganesh Bawaskar wrote:
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I think OS has provided only the interrupts for unusual conditions like PRIVILEGE VIOLATION, DIVIDE BY ZERO, BUS ERROR etc.
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No, that's wrong. It is the matter of the Os to provide all exception vectors.
Ganesh Bawaskar wrote:
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Let us consider a case, DIVIDE BY ZERO exception/interrupt occur, and processor goes to the 14H location (for 68K) where put the starting address of ISR as 00070020H. So it jumps to memory location 00070020H and start executing the instructions from here till it finds RTE instruction to return from the ISR. So we can write any instructions starting from 00070020H.
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The divide by zero exception vector jumps into the Os, where the exception is decoded, and then decided what to do about it. Possible reactions are terminating the program, jumping into a user-provided service routine, or ignoring the exception. Possibly some others. But no, the user should never write into the vector basis table. And never can. It resides in supervisor memory.
Ganesh Bawaskar wrote:
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so do you got my point what i mean to say?
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No.
Ganesh Bawaskar wrote:
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Processor doesnt have ISRs for any of the exceptions.
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Yes, it does.
Ganesh Bawaskar wrote:
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Its our duty to put the starting address of the ISR and write the ISR to tell the processor what is to be done if such interrupt/exception occurs.
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No, that's the matter of an operating system. It's the job of the designer of the Os to handle the exception, and then, in a second stage, to possibly allow the user to link in a custom exception handler.
Greetings,
Thomas
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Gunnar von Boehn
Germany
| | (Moderator)
Posts 5775
10 Mar 2011 08:43
| Ganesh Bawaskar wrote:
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There is a one flat memory space in our case as well.
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If its one flat space - why do you need FC0/1/2 then anyway?You should only need them if you want to implement physically seperate address spaces. And or for bus debugging.
But if you implement you chip in VHDL you have more powerful debugging means than using external state bits. Therefor I do not see the need for the FC bits anymore in VHDL 68K cores.
Ganesh Bawaskar wrote:
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As you quoted:
FC0 FC1 Instruction Read
Stage 1: 0 1 1 1
Stage 4: * * 0 1
Stage 6: 1 0 0 0
FC2 is set as your SupervisorBit in SR.
Please mind that Stage 4 can do two types of access!
Access to all normal EA : FC1=1/FC0=0
Access to PC-Relative : FC1=0/FC0=1
--------
I think
FC2 is used to indicate user/supervisor
FC1 is used to indicate instruction fetch
FC0 is used to indicate data fetch
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This is a good question. The FC pins can be used for satus debugging.
But could IMHO also be used for seperating the Adress spaces. To be frank - I never saw a system doing full Harvard,
so my knowledge comes only from reading and not from doign in this reagrd. I think that bits are not meant for what the data is used, but from where to get it. Then the idea of FC0/1/2 is to extend your address space.
The 68K does support the full harvard architecture.
The idea behind the FC:0/1/2 is to quadrouple the area.
Therefore you can in theory have 64MB by seperates user and supervisor and/or seperated data and instruction memory spaces
This is my understanding of the FC pins.
But frankly I think most people/systeme will not use nor need them. Cheers
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Ganesh Bawaskar
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Posts 20
10 Mar 2011 09:18
| As 68k was generating these signals and these signals are used in the hardware (on the entire board). and we dont want to change the hardware as well as f/w. we want to implement the entire functionality in the FPGA Now i understood when to generate FC2/1/0 as 101/010/001/110
but when its going to generate FC2/1/0 as 111?
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Thomas Richter
Germany
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Posts 1425
10 Mar 2011 09:52
| Gunnar von Boehn wrote:
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The idea behind the FC:0/1/2 is to quadrouple the area.
Therefore you can in theory have 64MB by seperates user and supervisor and/or seperated data and instruction memory spaces.
This is my understanding of the FC pins.
But frankly I think most people/systeme will not use nor need them.
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IIRC, the Atari ST used the user/supervisor pin to hide its hardware from user programs. I actually like this idea, user code shouldn't access the hardware.Greetings,
Thomas
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Thomas Richter
Germany
| | (MX-Board Owner)
Posts 1425
10 Mar 2011 09:54
| Ganesh Bawaskar wrote:
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As 68k was generating these signals and these signals are used in the hardware (on the entire board). and we dont want to change the hardware as well as f/w. we want to implement the entire functionality in the FPGA
Now i understood when to generate FC2/1/0 as 101/010/001/110
but when its going to generate FC2/1/0 as 111?
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IIRC, its part of the interrupt acknowledge. That is, the 68K generates this function code if it requests an interrupt vector. You could then either provide your own (that is, *not* an autovector, but the hardware could provide one), or not acknowledge the request and let the CPU fetch the autovector from the vector base table.But that's from memory, I might be wrong. Greetings, Thomas
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Ganesh Bawaskar
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Posts 20
10 Mar 2011 10:11
| Thomas Richter wrote:
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No, that's the matter of an operating system. It's the job of the designer of the Os to handle the exception, and then, in a second stage, to possibly allow the user to link in a custom exception handler.
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You mean to say for every exception there is a microcode handler which executes when exception occurs and for custom handling we can write our code
Please can you tell me what exactly happens once we apply reset?
i mean a series of actions till 68k switches to user mode
Thanks Thomas for all your help
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Ganesh Bawaskar
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Posts 20
10 Mar 2011 10:13
| As you quoted:
No, that's the matter of an operating system. It's the job of the designer of the Os to handle the exception, and then, in a second stage, to possibly allow the user to link in a custom exception handler.
--------- You mean to say for every exception there is a microcode handler which executes when exception occurs and for custom handling we can write our code
------ Please can you tell me what exactly happens once we apply reset?
i mean a series of actions till 68k switches to user mode Thanks Thomas for all your help
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Thomas Richter
Germany
| | (MX-Board Owner)
Posts 1425
10 Mar 2011 11:05
| At reset, the following happens: The CPU enters supervisor state, resets the vector base register. It reads then (supervisor state) the initial PC from address zero, and the initial stack from address 4 (IIRC). Apparently, ROM must be mapped in there at these addresses, and hence the autovectors are also located in ROM. In the Amiga kickstart, the CPU then jumps into the ROM, and disables the ROM mirror to address zero, thus RAM appears at zero. It then fills out the autovectors, and points them to the service routines of the Os. These are plain simple 68K assembly routines, there is no microcode there whatsoever.
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Ganesh Bawaskar
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Posts 20
10 Mar 2011 12:14
| Thanks Thomas.
Its really a great help
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Fabian Nunez
USA
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Posts 312
10 Mar 2011 17:27
| Ganesh Bawaskar wrote:
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basically its a product continuation project. Earlier boards use 68k, so without affecting the F/W we have to redesign the entire board.
So we decided to implement the 68k VHDL softcore for this.
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I think you guys may need to reconsider that decision. The 68000 is not a simple CPU by any means, so unless the firmware is several dozen megs of uncommented, hand-written assembler I'm not convinced it would be cheaper to just rewrite it rather than writing a 68000 in VHDL from scratch - especially one that needs to model even little-used signals like FC0-FC2. If you're using an FPGA big enough to hold a 68k plus whatever you had in there before you're already making changes to the circuit board, so you can use a faster microcontroller as well. You should look at one of the open source 68000 cores even if you don't plan using it, just to see what you're getting yourselves into.
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Jakob Eriksson
Sweden
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Posts 1097
10 Mar 2011 19:18
| There are several free open source 68000 CPUs already. Check out Minimig, SUSKA Atari CPU and OpenCores 68000 CPU.
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Ganesh Bawaskar
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Posts 20
11 Mar 2011 04:58
| Fabian Nunez wrote:
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I think you guys may need to reconsider that decision. The 68000 is not a simple CPU by any means, so unless the firmware is several dozen megs of uncommented, hand-written assembler I'm not convinced it would be cheaper to just rewrite it rather than writing a 68000 in VHDL from scratch - especially one that needs to model even little-used signals like FC0-FC2. If you're using an FPGA big enough to hold a 68k plus whatever you had in there before you're already making changes to the circuit board, so you can use a faster microcontroller as well. You should look at one of the open source 68000 cores even if you don't plan using it, just to see what you're getting yourselves into.
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Yah thats true. But 68k and 68020 is used on around 18 boards. if we can make a softcore for these processors then this would be a solution for all.
we are thinking of one more alternative of using 32-bit microcontroller from innovasic which supports nearabout all 68k instructions. few features which it doesnt support can be implemented/handled by FPGA.
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Ganesh Bawaskar
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Posts 20
11 Mar 2011 05:21
| 68k has few bus cycles like read,write,address error,bus error and various bus arbitration cycles.
Does anybody have an idea how to implement these 68k bus cycles in 68k softcore?
There are various signals (like A1/0, SIZ1/0, FC2/1/0, DBEN, ECS, OCS, R/W etc ) which needs to be generated for each and every cycle.
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