| 68050/68070 Vs ARM Cortex | page 1 2
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Cesare Di Mauro
Italy
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Posts 528
15 Oct 2010 08:03
| Gunnar von Boehn wrote:
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Cesare Di Mauro wrote:
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Unfortunately, index address extension word(s) need to be read before knowing the exact instruction size.
That was the major issue for the 68020+ decoder.
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This is true.
This gave us headaches for quite a while.
But we solved this with the 68050 design.
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Have you made use of I-Cache "tags" to mark istructions begin/end?
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Gunnar von Boehn
Germany
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Posts 5775
15 Oct 2010 08:54
| Cesare Di Mauro wrote:
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Gunnar von Boehn wrote:
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Cesare Di Mauro wrote:
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Unfortunately, index address extension word(s) need to be read before knowing the exact instruction size.
That was the major issue for the 68020+ decoder.
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This is true.
This gave us headaches for quite a while.
But we solved this with the 68050 design.
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Have you made use of I-Cache "tags" to mark istructions begin/end?
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Yes.
You need to do something like this to get reach high clockrates with the 020 modes and to reach high clockrates in combination with super scalarity on the 68K. By reusing this tag feature we could add the proposed new address modes using prefixes without any drawbacks.
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Megol .
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Posts 690
15 Oct 2010 11:29
| Gunnar von Boehn wrote:
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Cesare Di Mauro wrote:
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Unfortunately, index address extension word(s) need to be read before knowing the exact instruction size.
That was the major issue for the 68020+ decoder.
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This is true.
This gave us headaches for quite a while.
But we solved this with the 68050 design.
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The only real solution is massive parallel decoders for length determination, caching the instruction lengths are more of a hack.
(IMHO - no negative implications with the word hack btw)
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Cesare Di Mauro
Italy
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Posts 528
15 Oct 2010 13:25
| It isn't an hack: it's a well known and used technique by Intel and AMD in their x86 implementations.
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Megol .
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Posts 690
15 Oct 2010 16:12
| Cesare Di Mauro wrote:
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It isn't an hack: it's a well known and used technique by Intel and AMD in their x86 implementations.
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It's still a hack. It's a hack as it doesn't solve the problem but merely circumvent it. Branch prediction is a hack too for the same reason. Dynamic memory disambiguation too.
Intel have never used it since Pentium Pro and AMD will not use it in their planned future cores AFAIK. It's cheaper power-wise to recalculate instruction limits instead of storing it.
(Again: nothing negative meant)
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Cesare Di Mauro
Italy
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Posts 528
15 Oct 2010 20:08
| Megol . wrote:
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Cesare Di Mauro wrote:
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It isn't an hack: it's a well known and used technique by Intel and AMD in their x86 implementations. |
It's still a hack. It's a hack as it doesn't solve the problem but merely circumvent it. |
It's questionable. If it works, I consider it a solution. :P
| Branch prediction is a hack too for the same reason. |
Hum. Do you prefer predication (ARM? Or Itanium?)
| Dynamic memory disambiguation too. |
It's a good idea. :)
| Intel have never used it since Pentium Pro |
That was logical: the Pentium was able to execute at most two (serial) instructions.The Pentium Pro raised the number to three, OoO, so it needed a more efficient way to know how many and what kind of instructions will have to execute.
and AMD will not use it in their planned future cores AFAIK. It's cheaper power-wise to recalculate instruction limits instead of storing it.
(Again: nothing negative meant) |
That's a news for me. I have to find some information about it. :P
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Do you have questions about the Natami?