Well, with shrinking process geometries you can fit more chips on a wafer and thus produce the same number of chips with less wafer starts, i.e. faster and cheaper. There are two effects having opposite directions but yes, it seems that the process costs go up faster than the savings.

While this has been predicted for a long time, process development might indeed come to an end (or rather approach an upper limit in an asymptotic manner). Beyond 10 nm I can hardly see how you could get any devices to work that follow the principles of transistors as we have known them through the last decades. But that has been said many times before. However, these past false predictions do not generally prejudice newer ones. After all, the diameter of an atom does give a hard boundary. And since we don't want our transistors to randomly diffuse away at temperatures above 0 Kelvin, we will need at least several atoms. Gates of common MOS transistors are about 2 nm and hence only a few atomic layers thick. Perhaps less than 10 nm channel length will be possible, but then there really is hardly anything more to shrink...

That isn't quite the same. If you really want to have more than one layer of transistors on a chip, you will need epitaxial growth to add further layers. The problem is that such layers tend to be more uneven than the Rocky Mountains in comparison to transistor dimensions. Stacking of chips has been done but this is very costly and usually more of a way to save chip housing, PCB space and to decrease parasitic capacitances in the interconnection.

Full startup (complete mask sets etc) for 90nm designs today are in order of 200000$. Test-runs (shared mask) are in order of 10000$, depends of IC size.

Hell lot but if you can sell 50000 pieces (this is medium volume) for 20$  you still can earn a lot.

finally wafer processing costs are lower on that nodes (below $3000 per wafer), device parameters variability is lower and speed not that different.

For small sized IC (still like million of gates in 90nm process) you can fit in 1$/chip production costs.

So what a problem?

There are lot of digital chips produced now and designed now for 90nm or even 180-250nm nodes!!

Some even produce billions of "outdated" technology chips.

see EXTERNAL LINK 
Microcontroller manufacturer that buys out "outdated" fabs and then
produce enormous amount of microcontrollers.

Actually shrinking geometry below current 22nm process (intel terminology, actually 40-45nm half-pitch) doesn't make any logical sense, but will be 2-3 generations more done to show up on market.

Shrinking DRAM feature size more make sense. DRAM chips by definition are billion-volume products, and getting to smaller geometries are far cheaper as DRAM structures are repetitive.

DRAM may go below 10nm half-pitch.

FLASH are already on dead end. you may make them smaller but endurance falls exponentially. FLASH is only great for reprogrammable large read-only storage.

SSD "disks" are good for read-mostly workload. Newer SSD will tolerate few times less writes.

Putting a little more brain on problem is smarter than putting 10 billion more transistors.